Suman Datta is an Associate Professor in the Department of Electrical Engineering at the Penn State University with a joint appointment in the Penn State Materials Research Institute. Suman received his Bachelors in Electrical Engineering from the Indian Institute of Technology, Kanpur, India, in 1995 and his Ph.D. in Electrical & Computer Engineering from the University of Cincinnati, USA, in 1999. He is exploring new materials, novel nanofabrication techniques, new classical and non-classical device structures for CMOS “enhancement” as well as for CMOS “replacement” for future energy efficient, high performance and fault-tolerant information processing systems. He is also interested in exploring novel energy conversion devices harnessing nanoscale properties of nanostructures. Currently, he holds the Joseph Monkowsky Professorship for Early Faculty Career Development.
Prior to joining Penn State, he was a Principal Engineer in the Advanced Transistor and Nanotechnology Group at Intel Corporation. Suman is an internationally recognized expert in device modeling, fabrication and characterization specializing in advanced silicon and compound semiconductor based devices for ultra low-power logic and embedded memory applications. He was the Intel device lead in the joint Intel-QinetiQ research team that demonstrated the world’s first enhancement mode and depletion mode indium antimonide based quantum-well transistors operating at room temperature with record power-delay product. This work, presented at the 2005 International Electron Device Meeting (IEDM), sparked world-wide interest in pursuing heterogeneous integration of high-mobility narrow-gap materials on silicon platform for low-power, high-speed digital logic applications.
 Suman reported on the first experimental evidence of the additive effect of metal gate plasmons screening and channel strain engineering in mitigating the remote soft optical phonon induced mobility degradation in high-k/metal-gate CMOS transistors. This work, presented at the 2003 International Electron Device Meeting (IEDM), provided the first experimental feasibility demonstration of high-performance strained-channel high-k/metal-gate CMOS transistors. He received the 2003 Intel Achievement Award (the highest technical honor at Intel) for “developing the world’s first high-K/metal gate CMOS transistors with record-setting performance”.
Suman investigated the device physics, particularly the transport properties and the electrostatic robustness, of non-planar, multiple gate transistors called the “Tri-Gate Transistors” for “extreme scalability”, and its implications on logic and SRAM circuit design. His contribution was recognized with a 2002 Divisional Recognition Award from the Intel Logic Technology Development Group for “invention and successful demonstration of high performance Tri-gate CMOS transistors”.
He has published over 25 journal articles over the last 9 years and holds 40 US and international patents related to advanced process technologies and transistor architecture. He is a Senior Member of the IEEE Electron Devices Society.

Selected Publications

2007

S. Datta, G. Dewey, J. M. Fastenau, M. K. Hudait, D. Loubychev, W. K. Liu, M. Radosavljevic, W. Rachmady and R. Chau, “Ultrahigh-Speed 0.5 V Supply Voltage In0.7Ga0.3As Quantum-Well Transistors on Silicon Substrate”, IEEE Electron Device Letters, vol. 28, no. 8, pp. 685 (2007)

S. Datta, “III-V field-effect transistors for low power digital logic applications” Journal of Microelectronic Engineering, vol. 84 , no. 9-10, pp. 2133-2137 (2007)

R. Chau, B. Doyle, S. Datta, K. Kavalieros and K. Zhang, “Integrated nanoelectronics for the future”, Nature Materials, vol 6, pp. 810-812 (2007)

C. Y. Chang, H. T. Hsu, E. Y. Chang, C. I. Kuo, S. Datta, M. Radosavljevic, M.   Miyamoto, G.W. Y. Huang “Investigation of Impact Ionization in InAs-Channel HEMT for High-Speed and Low-Power Applications”, IEEE Electron Device Letters, vol. 28, no. 10, pp. 856-858 (2007)

T. Ashley, L. Buckle, S. Datta, M.T. Emeny, D.G. Hayes, K.P. Hilton, R. Jefferies, T. Martin, T.J. Phillips, D.J. Wallis, P.J. Wilding and R. Chau, “Heterogeneous InSb quantum well transistors on silicon for ultra-high speed, low power logic applications”, Electronics Letters, vol. 43 no. 14 (2007)

2006

J. Kavalieros, B. S. Doyle, S. Datta, G. Dewey “Tri-Gate Transistor Architecture with High-k Gate Dielectrics, Metal Gates and Strain Engineering,” Digest of Technical Papers VLSI Technology Symposium, pp.62-63 (2006)

2005

R. Chau, S. Datta, M. Doczy, B. S. Doyle, B. Jin, J. Kavalieros, A. Majumdar, M. Metz and M. Radosavljevic “Benchmarking nanotechnology for high-performance and low-power logic transistor applications,” IEEE Transactions on Nanotechnology, vol 4, no. 2, pp. 153-158 (2005)

S. Datta, T. Ashley, J. Brask, L. Buckle, M. Doczy, M. Emeny, D. Hayes, K. Hilton, R. Jefferies, T. Martin, T. Phillips, D. Wallis, P. Wilding and R. Chau, “85nm gate length enhancement and depletion mode InSb quantum well transistors for ultra high speed and very low power digital logic applications”, International Electron Devices Meeting (IEDM) Technical Digest, pp. 763-766 (2005)

R. Chau, J. Brask, S. Datta, G. Dewey, M. Doczy, B. Doyle, J. Kavalieros, B. Jin, M. Metz, A. Majumdar and M. Radosavljevic, “Application of high-K gate dielectrics and metal gate electrodes to enable silicon and non-silicon logic nanotechnology,” Journal of MicroElectronic Engineering, vol. 80, no 17, pp. 1-6 (2005)

2004

R. Chau, S. Datta, M. Doczy, B. Doyle, J. Kavalieros and M. Metz, “High-K/Metal-Gate Stack and its MOSFET Characteristics,” IEEE Electron Device Letters, vol. 25, no. 6, pp. 408-410 (2004)

T. Ashley, A. Bares, L. Buckle, S. Datta, A. Dean, M. Emeny, M. Fearn, D. Hayes, K. Hilton, R. Jefferies, T. Martin, K. Nash, T. Philips, W. Tang, P. Wilding and R. Chau, “Novel InSb-based Quantum Well Transistors for Ultra-High Speed, Low Power Logic Applications,” Proceedings 7th International Conference on Solid-State and Integrated Circuits Technology (ICSICT), Beijing, China, pp. 2253-2256 (2004)

2003

R. Chau, B. Boyanov, B. Doyle, M. Doczy, S. Datta, S. Hareland, B. Jin, J. Kavalieros, and M. Metz, "Silicon Nano-transistors for Logic Applications," Physica E, Low-Dimensional Systems and Nanostructures, vol. 19, no 1-2, pp.1-5 (2003)

S. Datta, G. Dewey, M. Doczy, B. Doyle, B. Jin, J. Kavalieros, M. Metz, N. Zelick and R. Chau, “High mobility Si/SiGe strained channel MOS transistors with HfO2/TiN gate stacks”, International Electron Devices Meeting (IEDM) Technical Digest, pp. 28.1.1 - 28.1.4 (2003)

B.S. Doyle, S. Datta, M. Doczy, S. Hareland, B. Jin, J. Kavalieros, T. Linton, A. Murthy, R. Rios, and R. Chau, "High Performance Fully-Depleted Tri-Gate CMOS Transistors," IEEE Electron Device Letters, vol. 24, no. 4, pp.263-265 (2003)

2002

R. Chau, B. Doyle, J. Kavalieros, D. Barlage, A. Murthy, M. Doczy, R. Arghavani, and S. Datta, "Advanced Depleted-Substrate Transistors: Single-gate, Double-Gate and Tri-gate," Extended Abstracts of the International Conference on Solid-State Devices and Materials (SSDM), pp. 68-69 (2002)

2000

S. Datta, K. P. Roenker, M. M. Cahay and L. M. Lunardi, “Analytical Modeling of Pnp InP/InGaAs Heterojunction Bipolar Transistors,” Solid-state Electronics, vol. 44, no. 7, pp. 1331-1333 (2000)

S. Datta, K. P. Roenker and M. M. Cahay, “A Gummel-Poon Model for Pnp Heterojunction Bipolar Transistors with a Compositionally Graded Base,” Solid-state Electronics, vol. 44, no. 6, pp. 991-1000 (2000)

1999

S. Datta,  K. P. Roenker and M. M. Cahay, “Emitter Series Resistance Effect of Multiple Heterojunction Contacts for Pnp Heterojunction Bipolar Transistors,” Solid-State Electronics, vol. 43, no. 7, pp. 1299-1305 (1999)

S. Datta,  K. P. Roenker and M. M. Cahay, “Hole Transport and Quasi-Fermi Level Splitting at the Emitter-Base Junction in Pnp Heterojunction Bipolar Transistors,” Journal of Applied Physics, vol 85, no 3, pp. 1949-1955 (1999)

S. Datta, K. P. Roenker and M. M. Cahay, “Implications of Hole versus Electron Transport Properties for High Speed Pnp Heterojunction Bipolar Transistors,” Solid-state Electronics, vol 43 no 1, pp. 73-80 (1999)

1998

S. Datta, S. Shi, K. P. Roenker and M. M. Cahay and W. E. Stanchina, “Simulation and Design of InAlAs/InGaAs Pnp Heterojunction Bipolar Transistors,” IEEE Transactions on Electron Devices vol 45, no 8, pp. 1634-1643 (1998)

S. Datta, K. P. Roenker and M. M. Cahay, “A  Thermionic-Emission-Diffusion Model for a Graded Base Pnp Heterojunction Bipolar Transistors,”  Journal of Applied Physics, vol 83, no 12, pp. 8036-8045 (1998)

.

Last Updated: December 4, 2007
EE Webmaster