Publications
2011
· F. Moradi, S. K. Gupta, G. Panagopoulos, H. Mahmoodi, D. T. Wisland and K. Roy, “Asymmetrically-doped (AD) FinFET for Low Power Robust SRAMs”, IEEE Transactions on Electron Devices, vol. 58, no. 12, pp: 4241-4249, December 2011.
· S. K. Gupta, S. P. Park and K. Roy, “Tri-mode Independent Gate FinFETs for Dynamic Voltage/Frequency Scalable 6T SRAMs”, IEEE Transactions on Electron Devices, vol. 58, no. 11, pp: 3837-3846, November 2011.
· S. Raghunathan, S. K. Gupta, H. Markandeya, P.P. Irazoqui and K. Roy, “Ultra-Low-Power Algorithm design for Implantable Devices- Application to Epilepsy Prostheses”, Journal of Low Power Electronics and Applications, vol. 1, no. 1, pp: 175-203, May 2011 (Invited).
· N. N. Mojumder, S. K. Gupta, S. H. Choday, D. E. Nikonov and K. Roy, “Three-Terminal Dual-Pillar STT-MRAM Device for High-Performance Robust Memory Applications," IEEE Tranactions on Electron Devices, vol. 58, no. 5, pp: 1508-1516, May 2011.
· A. Goel, S. K. Gupta and K. Roy, “Asymmetric Drain Spacer Extension (ADSE) FinFETs for Low Power and Robust SRAMs”, IEEE Transactions on Electron Devices, vol. 58, no. 2, pp: 296-308, Feb 2011.
Conference Proceedings
· S. K. Gupta, S. H. Choday and K. Roy, “Exploration of Device-Circuit Interactions in FinFET-based Memories for sub-15nm Technologies using a Mixed Mode Quantum Simulation Framework: Atoms to Systems”, International Electron Device Meetings, pp: 32.5.1-32.5.4, 2011.
· X. Fong, S. K. Gupta, N. N. Mojumder, H. Choday, C. Augustine, and Kaushik Roy, “KNACK: A Hybrid Spin-Charge Mixed-Mode Simulator for Evaluating Different Genres of Spin-Transfer Torque MRAM Bit-cells”, International Conference on Simulation of Semiconductor Processes and Devices, pp: 51-54, 2011.
· N. N. Mojumder, S. K. Gupta and K. Roy, “Dual Pillar Spin Transfer Torque MRAM with tilted magnetic anisotropy for fast and error-free switching and near-disturb-free read operations”, Device Research Conference, pp: 67-68, 2011.
· S. Dighe, S. K. Gupta, V. De, S. Vangal, N. Borkar, S. Borkar and K. Roy, “A 45nm 48-core IA processor with Variation-Aware Scheduling and Optimal Core Mapping” IEEE VLSI Circuit Symposium, pp: 250-251, 2011.
· M. Sharad, S. K. Gupta, S. Raghunathan, P. Irazoqui, K. Roy, " Ultra Low Power, LPF-Only DWT Architecture for an Epileptic Seizure Prosthesis Implant", Subthreshold Microelectronics Conference, 2011.