Publications
2012
Journal Articles
· S. K. Gupta, J. P Kulkarni, S. Datta and K. Roy, “Heterojunction Intra-band Tunneling (HIBT) FETs for Low Voltage SRAMs”, IEEE Transactions on Electron Devices, vol. 59, no.12, pp: 3533-3542, December 2012.
· S. K. Gupta, G. Panagopoulos and K. Roy, “NBTI in n-type SOI access FinFETs in 6T SRAM and its impact on cell stability and performance", IEEE Transactions on Electron Devices, vol. 59, no. 10, pp: 2603-2609, October 2012.
· M. Sharad, S. K. Gupta, S. Raghunathan, P. Irazoqui and K. Roy, " Low-Power Architecture for Epileptic Seizure Detection Based on Reduced Complexity DWT", ACM Journal on Emerging Technologies in Computing Systems, vol. 8, no. 2, June 2012.
Conference Proceedings
· S. K. Gupta and K. Roy, “Spacer Thickness Optimization for FinFET-based Logic and Memories: A Device-Circuit Co-design Approach”, Electro Chemical Society Symposium 2012 (Invited) (Rated amongst the top 8 papers in the entire conference).
· S. K. Gupta, J. P Kulkarni, S. Datta and K. Roy, “Dopant Straggle-Free Heterojunction Intra-band Tunneling (HIBT) FETs with Low Drain-induced Barrier Lowering/Thinning and Reduced Variation in OFF current”, Device Research Conference, pp: 55-56, 2012.
· D. Lee, S. K. Gupta and K. Roy “High-Performance Low-Energy STT MRAM Based on Balanced Write Scheme”, International Symposium on Low Power Electronics and Design (ISLPED), pp : 9-14, 2012.
· Y. Kim, S. K. Gupta, S. P. Park, G. Panagopoulos and K. Roy “Write-Optimized Reliable Design of STT MRAM” International Symposium on Low Power Electronics and Design (ISLPED), pp : 3-8, 2012. (Nominated for Best Paper Award).
· S. P. Park, S. K. Gupta, N. N. Mojumder, A. Raghunathan and K. Roy, “ Future Cache Design using STT MRAMs for Improved Energy Efficiency: Devices, Circuits and Architecture”, Design Automation Conference, pp: 492-497, 2012.
· S. K. Gupta, S. P. Park, N. N. Mojumder and K. Roy, “Layout-Aware Optimization of STT MRAMs”, Design Automation and Test in Europe Conference, pp: 1455-1458, 2012.