2017

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2014

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2008 & before

Patents

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2014

                                                                                                                                
Journal Articles

·  W. S. Cho, S. K. Gupta and K. Roy, “Device-Circuit Analysis of Double-Gate MOSFETs and Schottky-Barrier FETs: A Comparison Study for Sub-10nm Technologies”, to appear in IEEE Transactions on Electron Devices.

·  S. H. Choday, S. K. Gupta and K. Roy, “Write-Optimized STT-MRAM Bit-cells Using Asymmetrically Doped Transistors”, IEEE Electron Device Letters, vol. 35, no. 11, Nov 2014.

Conference Proceedings

·  S. Datta, R. Pandey, A. Agrawal, S. K. Gupta and R. Arghavani, “Impact of Contact and Local Interconnect Scaling on Logic Performance,” VLSI Tech. Symp. 2014. (Invited)

·  K. Ma, H. Lu, Y. Xiao, Y, Zheng, X. Li, S. K. Gupta, Y. Xie and V. Narayanan, “Independently-Controlled-Gate FinFET 6T SRAM Cell Design for Leakage Current Reduction and Enhanced Read Access Speed”, “ ISVLSI, 2014.

Invited Talks

· S. K. Gupta, "Low Power Robust Design of FinFET-based Circuits using a Technology-Circuit Co-optimization Approach”, 9th International Front-End Electronics (FEE) Conference, 2014.